The 3D V-NAND flash memory chip offers a 128-gigabit (Gb) density in a single chip, utilizing Samsung's so-called vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array.
Conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology has improved, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and costs.
"The new 3D V-NAND flash technology is the result of years of efforts to push beyond conventional ways of thinking and pursue much more innovative approaches in overcoming limitations in the design of memory semiconductor technology," said Samsung Electronics in a press release.
The new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid-state drives (SSDs).
After nearly 10 years of research on 3D V-NAND, Samsung now has more than 300 patent-pending 3D memory technologies worldwide, it said.
According to research firm IHS iSuppli, the global NAND flash memory market is expected to reach approximately US$30.8 billion by 2016, up from $23.6 billion in 2013.
According to the data compiled by another research firm iSupply, Samsung sold NAND flash memory chips worth $2.03 billion in the January-March period, accounting for 38.5 percent of the global market.
NAND flash memory chips are used for smartphones and other mobile devices.